The invention relates to integrated circuits and more particularly intelligent power management of the integrated circuit.
The application and acceptance of portable electronic devices has emphasized the importance of controlling and or optimizing power consumption. Actually controlling power consumption may be satisfied by adjusting the body voltage (i.e. the voltage magnitude between body and source) applied to transistors in an integrated circuit (IC). By increasing the body to source voltage, transistors achieve a higher threshold voltage, consume less static power but on the other hand provide lower performance. Conversely, lowering the body to source bias voltage reduces the transistor threshold voltages, providing higher performance but consuming greater static power. It is also known that the IC can be broken down into several partitions or sectors and the body voltage controlled on a partition by partition basis, see in this regard copending application entitled xe2x80x9cLow Powering Apparatus for Automatic Reduction of Power in Active and Standby Modesxe2x80x9d by Dean et al filed Jul. 21, 1998, Ser. No. 09/120,211, xe2x80x9cDevice and Method to Reduce Power Consumption in Integrated Semiconductor Devices Using a Lower Power Groggy Modexe2x80x9d, Bertin et al, filed on Sep. 24, 1998, Ser. No. 09/159,861 and xe2x80x9cASIC Low Power Activity Detector to Change Threshold Voltagexe2x80x9d, Dean et al, U.S. Ser. No. 09/159,898, filed on Sep. 24, 1998. The disclosures of these applications are incorporated herein by reference.
In the foregoing technology, the threshold voltage variation is implemented in integrated circuits involving Silicon-on-insulator (SOI) circuits. SOI circuits are circuits in which each element can be, or is, insulated from adjacent elements. However, as taught in co-pending application Ser. No. 08/866,674, Kalter et al, filed May 30, 1997 (the disclosure of which is incorporated herein by this reference), isolation from adjacent elements can also be obtained in so-called bulk silicon integrated circuits. Consequently, the integrated circuits described herein need not be limited to SOI integrated circuits. Rather, as described in the cited co-pending application, integrated circuits exhibiting the invention may also be implemented in bulk silicon.
Notwithstanding the foregoing, the art lacks a technology to allow optimizing power management in light of the actual repertoire of instructions applied to a partitioned integrated circuit.
The present invention provides an integrated circuit in which power is managed intelligently relative to the demands placed on the integrated circuit. In order to implement the foregoing the integrated circuit is designed with discrete functional units, each dedicated to a particular function or functions where each of the functional units has an independently controllable body voltage or threshold voltage (Vt). Consequently, each of the functional units can be operated at one of plural power levels depending on the body or threshold voltage applied thereto and independent of other functional units. Since the functional units have discrete functions, it is possible to correlate specific software instructions with one, or a set of, functional unit(s). Execution of the instruction at a high rate will require the correlated functional unit(s) to be in a high power state, other functional units need not be in a high power state.
For example, assume an IC embodying the invention had functional units dedicated to floating point arithmetic functions and a modem and the application program or program segment being executed involved a remote file transfer but no floating point operations. One could optimize the performance and power consumption of the IC for this program or program segment by reducing the power consumed by the floating point arithmetic functional unit to a minimum and raising the power consumption of the modem-related unit(s). Raising of the power level in the modem-related unit(s) is justified by the increase in performance while the power savings on the floating point arithmetic functional unit is obtained at no cost since the absence of floating point arithmetic operations means the performance of that functional unit or units is of no consequence to the execution of the application or program segment.
In general it is an object of the invention to control the power consumption of various functional units so as to present functional units in a high power state when instructions requiring their operation are to be executed and concomitantly to insure power is not wasted on functional units which are not involved in current instructions. The invention can be applied in various ways. For example, on power up all functional units may be powered to a high power state and units may be selectively depowered or run at reduced power to the extent current, or about to be executed, instructions do not require the function. Alternatively, units may be powered up or run at increased power levels when an instruction is identified which is about to be executed and requires the function. The power down of a functional unit which is operating at a high power state can depend on upcoming instructions, a time delay, or both.
In addition to the current or next instruction, the apparatus and method of the invention preferably should account for the delay occasioned in a transition of the power status of a functional unit from one power level to another. Thus, for example, in some cases it will be more efficient to maintain a high power status of a particular functional unit if the expected or nominal time gap between two instructions which require that functional unit is small relative to the delay in a power level transition.
The integrated circuit also includes a central processor which is coupled to the functional units to coordinate instruction execution. The central processor includes an intelligent power control which has at least a decode unit, a status table and a execution unit. In particular, the decode unit is responsive to the instruction stream. The decode unit maintains a correlation of instructions vs functional units. Having decoded an instruction, the decode unit can then identify a required one or ones of the functional units for executing that particular instruction. The status table indicates power status or power level data (which may be in the form of body voltage) for the functional units. Logically combining the output of the decode unit and the status table will indicate which, if any, of the functional units required for execution of a particular instruction are not at a high power state. This information is used in determining whether high speed operation for that instruction can be enabled.
An execution unit serves to allow execution of the instruction at the current processor speed if the information shows that power level status of the required functional units meets the requirement of the impending instruction(s).
In the event that one or more of the functional units do not have the required power status for execution at current processor speed, then the execution unit comes into play.
A first option for the execution unit is to stall (or delay) the instruction stream for a time sufficient for a change in the Vt level of the particular functional unit so that, after the delay, the particular functional unit will have the appropriate Vt for execution of the instruction.
The alternative to stalling the instruction stream is to maintain the instruction stream but to slow the process clock.
In some embodiments of the invention the functional units may have only two potential Vt levels; in other embodiments one or more of the functional units may have more than two potential Vt levels.
It should be understood that while different functional units have been described, one functional unit need not be totally independent of another and in some cases two different functional units may each include some common circuitry.
Preferably on chip reset, the functional units will default to the lowest power setting, represented by a high Vt.
Preferably when the power level for a given functional unit is increased, a timer or a timer function is initiated. The timer function is arranged to command return of a functional unit to lower power level on expiration. The timer function will expire on expiration of the timing period unless, within the timing period another request for a high power state of the functional unit is received which has the effect of reinitiating the timer function.
While the time period in some embodiments of the invention is fixed, in other embodiments of the invention the time period, before automatic reduction in functional unit power, is a programmable parameter.
In the event the stall option (to accommodate the delay occasioned by raising the power level of a functional unit) is undesirable, the instruction decode can be advanced in time relative to instruction execution, such as by a pre-fetch operation.
Thus in accordance with one embodiment the invention provides an integrated circuit chip including:
plural functional units subject to different power levels, only one of the power levels maximizing performance of the functional unit;
a central processor coupled to the functional units and operating at a current processor speed, the central processor including:
a decode unit for receiving and decoding an instruction and for identifying required ones of the functional units for executing the instruction;
a status table coupled to the functional units for indicating power level data of the functional units,
a logic unit responsive to the decode unit and to the status table to determine if a functional unit required for execution of an instruction is not at the one power level; and
an execution unit coupled to the logic unit for enabling execution of the instruction at the current processor speed if the power level data indicates that the required functional units have sufficient power levels.